1. Field of the Invention
The invention generally pertains to the field of input buffers. In particular, the present invention relates to input buffers having a stable trip point and to reference voltage generators which are responsive at least to process skew and supply voltage variations and that may be used in such input buffers. The present invention also pertains to methods of stabilizing trip points of input buffers over at least supply voltage variations and process skew.
2. Description of the Related Art
Input buffers, such as TTL input buffers, are interface circuits used to convert Transistor-Transistor Logic (TTL) signal levels to Complementary Metal Oxide Semiconductor (CMOS) signal levels. An ideal input buffer would have a trip point set to a nominal Vcc/2 for a low input voltage level (VIL) of 0 volts and a high input voltage level (VIH) of Vcc volts. Moreover, the trip point of such an ideal input buffer would be utterly stable and would be insensitive to process parameter skew, variations in the supply voltage Vcc, temperature and other manufacturing and environmental variations.
The performance of currently available input buffers only approximates that of such an ideal input buffer. A number of factors affect this performance and act alone and in combination to cause the trip point to vary from its nominal value of Vcc/2. A stable trip point, however, is important whenever set up and hold issues arise. For example, when latching an address in a register, the address must remain stable during the set up time interval as well as during the hold time interval. If the clock pulse arrives too late, i.e., in violation of hold time, the address to be latched will have disappeared and no address will have been latched. Conversely, should the clock pulse arrive too early, the address will not have stabilized yet and again no valid data will be latched within the register. The situation also holds in asynchronous circuits wherein the clock signal is typically an active low Write Enable (WEB) signal. In this case, data is not latched to a register but rather if the address changes too close to the WEB pin being asserted, the previously asserted address may be inadvertently overwritten with the new data.
This set up and hold window is typically very short. For example, the Set Up time interval (tsa) may be on the order of about 2.5 ns, whereas the Hold time interval (tha) may be on the order of about 0.5 ns. The total time interval during which the address to be latched must remain stable is the sum of these two intervals and is, therefore, only about 2.5 ns in duration. Variations in the input buffer trip point cut into this very narrow window and are, therefore, undesirable. The reason for this is illustrated in FIG. 7. The top signal in FIG. 7 is a clock pulse that is active on its positive going edge. In FIG. 7, the nominal trip point is set to be 1.25 volts. Then, a 250 mV variation in the trip point sets the new trip point at 1.5 V. This 250 mV variation, however, has a different effect upon positive going address pulses than it does on negative going address pulses. As shown in FIG. 7, the positive going address pulse will not reach the new 1.5 V trip point until later in time than will the negative going address pulse, the bottom signal in FIG. 7. In other words, the negative going address pulses will trip sooner than the positive going address pulse, thus making all falling edges faster and all rising edges slower. There is thus an asymmetry in the threshold point at which the signals trip.
If the slope of the pulse shown in FIG. 7 is 1V/ns, a variation in the trip point of 0.25 volts means 250 ps of time. From FIG. 7, it can be seen that the actual penalty for a 250 mV variation from the nominal trip point is 500 ps, as the positive going address pulse trips 250 ps after it would have at the nominal trip point, whereas the negative going address pulse trips 250 ps before it would have at the nominal trip point. Therefore, the Set Up and Hold window of 2.0 ns has been decreased by about 500 ps, fully one quarter of the available window. This decreased set up and hold window imposes additional and more severe timing constraints upon the operation and design of the input buffer, and may cause invalid data to be latched, depending on the magnitude of the variation in the trip point. Indeed, variations from the nominal trip point of greater magnitude quickly cut into the available set up and hold time interval. For example, a variation in the trip point that is only 50 mV greater than that illustrated in FIG. 7 reduces the Set Up and Hold window to only about 1.4 ns.
There are a number of reasons why the DC trip point of an input buffer would stray from nominal data book specifications. In the case of a CMOS buffer stage similar in design to that shown in FIG. 1, it has been found that variations in the magnitude of the Vcc supply and skew in a number of critical process parameters are responsible for about 70% and 20% of the trip point variation, respectively. The remaining 10% of the observed DC trip point variation is generally attributed to temperature fluctuations. The more important of these critical process parameters, in terms of contributing to trip point variations, are believed to be the critical dimensions, such as length and width, of the transistor gate (hereafter xe2x80x9cGate CDxe2x80x9d or xe2x80x9cPoly CDxe2x80x9d if polysilicon is used for the gate), the field oxide critical dimensions (hereafter xe2x80x9cFOM CDxe2x80x9d, for Field Oxide Mask Critical Dimensions) and the threshold voltage adjust dose (hereafter Vt adjust dose). Of these three process parameters, only the Vt adjust dose is believed to affect n channel and p channel FETs differently, although for narrow devices only, FOM CD can affect n and p channel devices differently, due to encroachment of field implants into the channel.
In submicron silicon gate processes, the speed of the device appears to be heavily dependent upon the gate etch step. When using polysilicon as the gate material, if the gate is under or over etched by as little as 10%, the speed of the device may be greatly affected. This is because the gate etch step defines the length of the channel L and the speed of the resultant device is proportional to the aspect ratio (W/L), where W is the width of the channel region and L its length. This (W/L) term affects the speed of the device, whether the device is operating in the linear region (also called the triode region) or is operating in the saturation mode. For example, the gate may have been over-etched during fabrication, resulting in shorter than expected n channel and p channel device channel lengths, thus causing these devices to have a greater Ids and speed than nominal.
The filed oxide is an isolation structure (generally a LOCOS or shallow trench isolation structure comprising silicon oxide) and defines the device width W of the (W/L) term by separating the active regions of CMOS devices. Variations in the FOM CD affect both n and p channel transistors.
The effects of the Vt adjust dose, however, are not shared equally among n channel FETs and p channel FETs. The Vt adjust dose raises the threshold voltage Vt by implantation of a p-type material such as boron into the channel region, before the polysilicon layer is formed. The boron dose is critical, as it has a direct effect upon Vt, which is directly related to the speed of the device. For example, a particular batch of wafers may have been given a slightly larger than nominal Vt adjust dose during fabrication. The p channel devices of such a batch may have a lower Vt then the n channel devices. A lower threshold voltage Vt results in higher drain to source current Ids for a given gate to source voltage Vgs. Higher Ids correlates directly with device speed.
The process parameters discussed above create so-called process corners in which p channel and n channel devices are termed slow, fast or typical. It is common to refer to these corners as ss, sf, ff and fs, where the first letter refers to the speed of the p channel device and the second letter refers to the speed of the n channel device. The fs corner, for example, refers to a situation wherein the p channel device is faster (higher Ids) than nominal and the n channel device is slower (lower Ids) than nominal. Likewise, the sf process corner refers to a slow p channel and a fast n channel device. Such a state might occur, for example, when the Vt adjust dose was lighter than it should have been, thus raising the threshold voltage Vt for the p channel device and lowering the Vt for the n channel device, making the p channel device slow (less Ids for a given Vgs) and the n channel device fast (more Ids for a given Vgs). Other process corner combinations are possible; including st, ts, ft and tf, where f signifies fast, s signifies slow and t denotes a typical device speed. The fs and sf corners are believed to have the greatest impact on the trip point skew of input buffers, as will be shown with reference to FIG. 1. The if, ss, st, ts, ft and tf process corners, while affecting the trip point of such input buffers, nevertheless have less impact thereon as do the fs and sf process corners, because of the relatively smaller disparity between the respective speeds between the p and n channel devices.
The skew in the process parameters, together with the variations in the Vcc supply, cause undesirable variations in the DC trip point of input buffers. What is needed, therefore, is an input buffer exhibiting increased stability over at least process parameter skew and variations in the supply voltage. What is also needed is a method of stabilizing input buffers, to reduce their sensitivity to variations in supply voltage and process skew corners.
It is, therefore, an object of the present invention to provide a buffer having a stable trip point.
It is yet another object of the present invention to provide a reference voltage generating circuit whose output swings about a nominal voltage responsive at least to process skew corners and variations in supply voltage.
It is a further object of the present invention to provide a method for stabilizing a trip point of an input buffer over at least process skew and variations in supply voltage.
In accordance with the above objects and those that will be mentioned and will become apparent below, the input buffer according to one embodiment of the present invention comprises:
an input stage, comprising at least one input node receiving a first signal, a first pull-up transistor, a first pull-down transistor, and an output node;
a control circuit configured to (i) couple the first pull-up transistor to a first supply voltage and/or decouple the first pull-up transistor from the first supply voltage, (ii) couple the output node to a second supply voltage and/or decouple the output node from the second supply voltage, or (iii) both (i) and (ii); and
a stabilizing circuit comprising first and second transistors, each in series with at least one of the first pull-up transistor and the first pull-down transistor.
The stabilizing circuit may comprise (i) a first p-channel transistor in a pull-up path and (ii) a first n-channel transistor in a pull-down path, each being independently coupled to at least one source/drain terminal of at least one of the first pull-up transistor and the first pull-down transistor. An output stage may be included and configured to generate an output signal in response to a voltage at the output node. The stabilizing circuit may be configured to (i) increase a pull down current through the source/drain terminal of the first pull-down transistor in response to a reference signal, (ii) decrease a pull down current through the source/drain terminals of the pull-down transistor in response to the reference signal, or (iii) both (i) and (ii). The pull-down path may comprise a second n-channel transistor configured to (i) couple a first output of the stabilizing circuit to the output node in response to the first signal at the input node, (ii) decouple the first output of the stabilizing circuit from the output node in response to the first signal at the input node, or (iii) both (i) and (ii). The stabilizing circuit may be configured to (i) increase a pull-up current through a first output of the control circuit and through the source/drain terminal of the first pull-up transistor in response to a reference signal, (ii) decrease the pull-up current through the first output of the control circuit and through the source/drain terminal of the first pull-up transistor in response to the reference signal, or (iii) both (i) and (ii).
The stabilizing circuit may be configured to (i) increase a pull-up current through a first output of the control circuit and through the source/drain terminal of the first pull-up transistor in response to a reference signal, (ii) decrease the pull-up current through the first output of the control circuit and through the source/drain terminal of the first pull-up transistor in response to the reference signal, or (iii) both (i) and (ii). The pull-up path may comprise a second p-channel transistor configured to (i) increase a pull-up current through a second output of the stabilizing circuit and through the output node in response to the first signal at the input node, (ii) decrease the pull-up current through the second output of the stabilizing circuit and through the output node in response to the first signal at the input node, or (iii) both (i) and (ii).
The input stage may further comprise a second pull-up transistor in parallel with the first pull-up transistor, configured to (i) couple a first output of the control circuit to the output node in response to the first signal at the input node, (ii) decouple the first output of the control circuit from the output node in response to the first signal at the input node, or (iii) both (i) and (ii); and a second pull-down transistor in parallel with the first pull-down transistor, configured to (i) couple the second supply voltage to the output node in response to the first signal at the input node, (ii) decouple the second supply voltage from the output node in response to the first signal at the input node, or (iii) both (i) and (ii). The first p-channel transistor and the first n-channel transistor may be coupled in parallel between the output node and one source/drain terminal of the first pull-up transistor.
The reference voltage may be generated by a reference voltage generating circuit configured to compensate for at least (i) variations in the first supply voltage and/or the second supply voltage, (ii) variations caused by process skew, or (iii) both (i) and (ii), by varying the reference voltage in response thereto. The reference voltage may be generated by a reference voltage generating circuit, comprising a control circuit configured to couple a first supply voltage to a first node in response to a control signal; a first compensation circuit comprising a first p-channel device and a first n-channel device defining a second node therebetween, the first compensation circuit providing a compensation signal at the second node in response to (i) a second supply voltage and (ii) a signal at the first node; and a second compensation circuit comprising a second p-channel device and a second n-channel device defining an output node therebetween, the second compensation circuit providing a reference voltage at the output node in response to (i) one of the first and second supply voltages, (ii) the signal at the first node, and (iii) the compensation signal.
The first p-channel transistor and the first n-channel transistor may be coupled in parallel between the output node and one source/drain terminal of the first pull-down transistor. The stabilizing circuit may further comprise a second p-channel transistor and a second n-channel transistor, each being coupled in parallel between the output node and one source/drain terminal of the first pull-up transistor. The first p-channel transistor and the first n-channel transistor may be coupled in parallel to one source/drain terminal of the first pull-down transistor.
According to another embodiment, the reference voltage generating circuit according to the present invention comprises:
a control circuit configured to couple a first supply voltage to a first node in response to a control signal;
a first compensation circuit comprising a first p-channel device and a first n-channel device defining a second node therebetween, the first compensation circuit providing a compensation signal at the second node in response to (i) a second supply voltage and (ii) a signal at the first node; and
a second compensation circuit comprising a second p-channel device and a second n-channel device defining an output node therebetween, the second compensation circuit providing a reference voltage at the output node in response to (i) one of the first and second supply voltages, (ii) the signal at the first node, and (iii) the compensation signal.
One of the first p-channel device and the first n-channel device maybe configured as a resistive device, and the other of the first p-channel device and the first n-channel device may be configured as a diode. One of the second p-channel device and the second n-channel device may be configured as a resistive device, and the other of the second p-channel device and the second n-channel device may comprise a transistor having a gate receiving the compensation signal.
According to another embodiment, the method of stabilizing a trip point of a buffer over variations in supply voltage and/or processing, the buffer comprising a pull-up path and a pull-down path, each path having a conductivity according to the present invention includes the steps of:
generating a reference voltage from first and second compensation circuits, each of the compensation circuits comprising a p-channel device and an n-channel device defining a node therebetween, the second compensation circuit providing the reference voltage at its node in response to at least one supply voltage and a signal at the node of the first compensation circuit, such that the reference voltage changes when the trip point differs from a nominal voltage; and
modulating at least one of the conductivities in response to a change in the reference voltage.
A step of generating the signal at the node of the first compensation circuit in response to at least one supply voltage and a control signal may be carried out, and the p-channel device and the n-channel device may be configured as resistive and/or diode-connected devices.